Samsung Samsung PN50A550 PN58A550 SchematicDiagram [SM] free download

File name Samsung_PN50A550_PN58A550_SchematicDiagram_[SM].pdf

Schematic Diagram 7. SchematicDiagram 7-1 CircuitDescription Logic Board Y Main Board X Main Board Display Row DRAM Data Driver PDP Panel Input X-Pulse Data Data Display Generator Controller Driver Processor Timing Y-Pulse Timing Controller Generator Scan Timing Address Buffer SMPS Board LVDS Main SMPS Main Board LVDS Image Audio Deinterlacer Trans Enhancer Processor Image CPU Video Speaker Decoder Decoder Out AC Power Scaler Tuner Source TMDS A/D Video Converter S/W Micom Recever SMPSBoard The SMPS used for the PDP has been designed to be efficient, compact and lightweight. For VS and VA outputs, a LLC converter has been used. For the other outputs, a Flyback converter has been used. LOGICBoard The logic circuit consists of a Logic Main Board and an Address Buffer Board. The Logic Main Board decodes the video signal encoded by the Video Board, outputs the ADDRESS data signal for each pattern and generates X and Y drive signals. The Address Buffer Board buffers and transfers the ADDRESS data output signal using TCP IC. - LVDS with built-in video signal processing (W/L, error diffusion, APC, FCR, etc.) applied and 1 ASIC chip. - Outputs the address Drive IC control and data signals to the Buffer Board. - Outputs the control signal for the X and Y Drive Boards. - Monitors major drive voltages (Micom Circuit Block); detects if a surge voltage has been applied and protects